18 Commits

Author	SHA1	Message	Date
SWivid	6d1a1e886a	formatting, sorting	2025-05-05 01:41:28 +08:00
SWivid	5f80fec160	fix speech_edit.py	2025-04-26 02:10:39 +08:00
tbxark	b2284b6cff	chore: Update the model checkpoint path to use the cache path.	2025-04-14 11:28:48 +08:00
SWivid	4ae5347282	pre-commit update and formatting	2025-03-21 23:01:00 +08:00
SWivid	ca6e49adaa	1.0.0 F5-TTS v1 base model with better training and inference performance	2025-03-12 17:23:10 +08:00
Phlo	f005f1565e	fix: typo in MPS PyTorch env variable	2025-02-18 03:28:44 -06:00
98440	964064094a	Added intel XPU support	2025-01-22 03:36:10 +08:00
ZhikangNiu	ec3bb7b62d	fix vocoder generate sample and #467	2024-11-23 18:20:28 +08:00
SWivid	cb8ce3306d	update. compatibility with mps device #477 thanks to @aboutmydreams	2024-11-17 18:57:28 +08:00
SWivid	0f80f25c5f	minor fix. speech_edit & eval_infer_batch	2024-11-17 06:25:07 +08:00
SWivid	315230210d	minor fix	2024-11-01 15:11:48 +08:00
ZhikangNiu	18e1ab508f	refactor: del global params and set vocos as default vocoder, add dtype check	2024-11-01 14:17:22 +08:00
ZhikangNiu	b180961782	refactor: more details about bigvgan, clear function definition	2024-11-01 11:02:39 +08:00
ZhikangNiu	36a4aad668	change some infer function to support two vocoder	2024-10-31 22:44:45 +08:00
ZhikangNiu	712d52772e	update Bigvgan vocoder and F5-bigvgan version, trained on Emilia ZH&EN, 1.25m updates	2024-10-31 20:06:36 +08:00
SWivid	f69a60287b	finish infer dependencies; update readmes	2024-10-25 03:48:53 +08:00
SWivid	8e0edfcf8f	final structure. prepared to solve dependencies	2024-10-24 00:55:41 +08:00
SWivid	8ed1beac1e	make a structure first	2024-10-24 00:07:14 +08:00